1. Field of the Invention
The present invention relates to semiconductor circuit design, and more particularly towards a circuit structure for timing operations performed by an issue unit.
2. Description of Prior Art
Arbitration logic is used to resolve situations where multiple parties contend for use of a shared resource. Such situations occur, for example, in instruction selection within microprocessor issue queues, and in shared bus architectures where multiple senders are contending for a shared bus.
With respect to wake up and select functionality in microprocessor issue queues, in prior work, different schemes have been evaluated in an attempt to reduce the time needed to detect when an instruction is ready for issue, and selecting one of several ready instructions for issue. There are at least two approaches, one splits the wake up and select into two different stages. This potentially increases the number of cycles or clocks per instruction (CPI) as dependent instructions cannot issue back to back. The CPI is the number of computer clock cycles that occur while a computer instruction is being executed. A second approach implements wake up and select as an atomic function in the same stage, thus enabling dependent instructions to issue back to back. This approach however, can increase the cycle time of the processor.
Therefore, it would be desirable to implement wake up and select as an atomic function in an efficient (fast) enough fashion as to keep it from affecting the processors cycle time. As power consumption is a design constraint in microprocessors, such a solution should also provide low power consumption. Therefore, a need exists for a low-power high-speed select arbitration device in integrated circuits.
According to an embodiment of the present invention, a select arbitration device is provided which determines participants to be granted. The select arbitration device includes at least two arbiters which receive ready request signals from a plurality of participants, each participant having a priority, and a plurality of any-request gates, wherein each any-request gate accepts the ready request signals from the participants, the any-request gate adapted to signal an arbiter of lower priority participants upon the ready request of a higher priority participant.
At least one arbiter is a precharged domino OR device. Each arbiter is one of a precharged domino OR device including a footing device, and a precharged domino OR device without a footing device. A grant output of each arbiter is gated by the ready signal of the participant.
At least one any-request gate is a precharged domino OR device. Each any-request gate is one of a precharged domino OR device including a footing device, and a precharged domino OR device without a footing device.
The select arbitration device includes a precharge signal of the any-request gate which is gated by an inhibit signal. The select arbitration device includes a latch device connected to a grant output signal of each arbiter and connected to a clock signal. The clock signal is gated by the ready request signal of the participant.
An evaluation of each any-request (anyreq) gate is triggered by the ready request signals and each arbiter is triggered by the ready request signals and a set of any-request signals. The set of any-request signals can be empty. An evaluation of each any-request gate is triggered by a precharge signal and each arbiter is triggered by a precharge signal. The precharge signal can be an evaluate signal.
According to an embodiment of the present invention, an integrated circuit is provided including a select arbitration device for selecting an instruction to issue, connected to an entry queue including a plurality of prioritized instructions, comprising a plurality of layers, wherein each layer further comprises a plurality of domino OR gate arbitration devices connected to a plurality of ready request signals of the entry queue and connected to a plurality of any-request (anyreq) signals corresponding to instructions of higher priority. The select arbitration device further includes a plurality of functional units for executing issued instructions, wherein each functional unit is connected to one layer of the select arbitration device.
Each precharged domino OR arbitration device of the select arbitration device further comprises a footing device for cutting off the path to ground while the domino OR gate arbitration device is precharging. Each precharged domino OR arbitration device of the select arbitration device is gated by the ready request signal of the corresponding instruction. Each domino OR gate arbitration device is triggered by the ready request signals and a set of any-request signals. The set of any-request signals can be empty. Each domino OR gate arbitration device is triggered by a precharge signal. The precharge signal can be an evaluate signal.
An any-request gate is a precharged domino OR device connected to a plurality of precharged domino OR arbitration devices for indicating to queue entries of lower priority that a higher priority queue entry has produced a ready request signal for issue. Each any-request gate is triggered either by the ready request signals or by a precharge signal. The precharge signal can be an evaluate signal.
According to an embodiment of the present invention, a method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domino OR gate arbitration device through an any-request device upon the ready request of a higher priority participant, and issuing the higher priority participant upon determining the higher priority participant to have a priority highest among participants ready for issue.
The method includes gating one of a precharge signal and an evaluate signal of the precharged domino OR gate arbitration device by the ready request of the participant. The method further includes latching a result of the domino OR gate arbitration device and a clock signal, and gating the clock signal by the ready signal of the participant.